DCB1M FPGA evaluation board emulates the coming DCB1M device. Used for test the communication over DC power line in noisy channels such as of vehicles at speeds of up to 1.4Mbps.


The DCB1M Evaluation Board contains all the required firmware for operation as a DC power line transceiver.

The logic is implemented in a FPGA that contains the modem and other logic required for its communication.

The Analog-front-end board consist of the analog circuitry, such as amplifiers, line protection network, filters that most of it will be embedded in the DCB1M ASIC.

A switching power supply provides the 3.3V required for the board operation from 10V to 35V DC power line.


The received phase modulated signal from the DC line passes through a protection network, input buffer and a passive filter to a comparator.

The FPGA logic decode the signal into bit stream message. The asynchronous or synchronous (UART/SPI) message output to the external host via JP1 HDO.

At the transmitter side, the external host input messages to the FPGA board via JP1 HDI pin either as an asynchronous UART or synchronous SPI bit stream. The message is buffered into packets, protected against errors, modulated and conducted over the DC power line.


  • Robust communication over DC or AC power line.
  • Bit rates of up to 1.3Mbps.
  • Variable error correction codes, to match the channel conditions.
  • Multiplex CSMA/CA mechanism .
  • Supports UART, SPI protocols.
  • Sleep Mode for low power consumption
  • Small size design.


  • Audio and Video streaming.
  • Local networtk for Internet of Things (IoT).
  • Data transfer over powerline
  • Redundant powerline network.
  • Security networks.


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