DCAN500 – CAN over powerline Evaluation Board

Quickly establish a CAN bus network over power line


  • Interface using the CAN bus protocol
  • Bit rates of up to 500Kbps.
  • CAN arbitration over the powerlines.
  • Built-in Modem, Error Correction and Synchronization.
  • Replace the CAN bus control wire.
  • Allows flexible network designs..
  • Sleep Mode for low power consumption


  • Battery Management Systems [BMS].
  • Adding a redundant CAN channel.
  • Replacing existing CAN bus wires

CAN-BUS communication over DC powerline can be achieved using the DCAN500 transciver. The DCAN500 was designed to transfer CAN messages over noisy DC Power Line using the DC-BUS technology. It becomes a new physical layer of CAN bus network over the powerline for robust communication between electronic modules sharing a common DC power supply line. The DCAN500 FPGA Evaluation Board (EVB) is designed to emulate and test the operation of the DCAN500 device in a system. Multiple DCAN500 boards can communicate over a vehicle’s DC power line using the CAN protocol. The EVB contains all the required hardware for device operation such as a line protection network, passive filters and a power supply. The board performs the CAN protocol over DC power lines at data rates of up to 500Kbps. The EVB may be connected directly to a CAN host (CAN-Controller) through its JP1 Host I/O connector. This innovative solution allows low cost overall CAN implementation, combining power and data over the same cable, withstanding the hostile DC lines impulse noises. The DCAN500 EVB has an on-board switching power supply for operation between 10V and 50V. The average current consumption is in the range of 80mA. The EVB has 3 LEDs for diagnostics and indication.

DCAN250 EVB Block diagram
                                                DCAN500 Evaluation board blocks

The received data signal from the DC line passes through a protection network, input buffer and a passive filter (selectable by a multiplexer ) to a comparator. The FPGA receives the digital signal, where it is decoded, processed and transferred to J1 HDO as an asynchronous bit stream. This data is connected directly to a host through connector J1. On the transmitter side, the host sends data to the FPGA via J1 HDI pin as an asynchronous bit stream. The sent data is buffered into packets, modulated and conducted over the DC power line.

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